;; Function f (f) starting the processing of deferred insns ending the processing of deferred insns df_analyze called scanning new insn with uid = 109. verify found no changes in insn with uid = 109. deleting insn with uid = 81. Building IRA IR starting the processing of deferred insns ending the processing of deferred insns df_analyze called df_worklist_dataflow_doublequeue:n_basic_blocks 7 n_edges 8 count 8 ( 1.1) df_worklist_dataflow_doublequeue:n_basic_blocks 7 n_edges 8 count 8 ( 1.1) init_insns for 279: (insn_list:REG_DEP_TRUE 68 (nil)) init_insns for 285: (insn_list:REG_DEP_TRUE 109 (nil)) Pass 0 for finding pseudo/allocno costs a28 (r289,l1) best GR_REGS, cover GR_AND_ACC_REGS a8 (r289,l0) best GR_REGS, cover GR_AND_ACC_REGS a27 (r288,l1) best GR_REGS, cover GR_AND_ACC_REGS a11 (r288,l0) best GR_REGS, cover GR_AND_ACC_REGS a9 (r287,l0) best GR_REGS, cover GR_AND_ACC_REGS a2 (r285,l0) best GR_REGS, cover GR_AND_ACC_REGS a1 (r284,l0) best PIC_FN_ADDR_REG, cover GR_AND_ACC_REGS a3 (r283,l0) best GR_REGS, cover GR_AND_ACC_REGS a5 (r281,l0) best GR_REGS, cover GR_AND_ACC_REGS a30 (r279,l1) best GR_REGS, cover GR_AND_ACC_REGS a31 (r278,l1) best GR_REGS, cover GR_AND_ACC_REGS a32 (r277,l1) best GR_REGS, cover GR_AND_ACC_REGS a29 (r275,l1) best GR_REGS, cover GR_AND_ACC_REGS a15 (r273,l0) best GR_REGS, cover GR_AND_ACC_REGS a16 (r272,l0) best GR_REGS, cover GR_AND_ACC_REGS a17 (r271,l0) best GR_REGS, cover GR_AND_ACC_REGS a20 (r270,l0) best GR_REGS, cover GR_AND_ACC_REGS a26 (r269,l1) best GR_AND_ACC_REGS, cover GR_AND_ACC_REGS a4 (r269,l0) best GR_REGS, cover GR_AND_ACC_REGS a25 (r268,l1) best GR_REGS, cover GR_AND_ACC_REGS a19 (r268,l0) best GR_REGS, cover GR_AND_ACC_REGS a10 (r267,l0) best GR_REGS, cover GR_AND_ACC_REGS a12 (r266,l0) best GR_REGS, cover GR_AND_ACC_REGS a18 (r265,l0) best GR_REGS, cover GR_AND_ACC_REGS a24 (r264,l1) best GR_AND_ACC_REGS, cover GR_AND_ACC_REGS a6 (r264,l0) best GR_REGS, cover GR_AND_ACC_REGS a23 (r262,l1) best GR_REGS, cover GR_AND_ACC_REGS a14 (r262,l0) best GR_REGS, cover GR_AND_ACC_REGS a22 (r257,l1) best GR_AND_ACC_REGS, cover GR_AND_ACC_REGS a7 (r257,l0) best GR_REGS, cover GR_AND_ACC_REGS a21 (r250,l1) best GR_REGS, cover GR_AND_ACC_REGS a13 (r250,l0) best GR_REGS, cover GR_AND_ACC_REGS a0 (r234,l0) best GR_REGS, cover GR_AND_ACC_REGS a0(r234,l0) costs: MD1_REG:1566,1566 MD_REGS:1566,1566 ACC_REGS:1566,1566 GR_AND_MD0_REGS:522,522 GR_AND_MD1_REGS:1566,1566 GR_AND_ACC_REGS:1566,1566 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:1044,1044 MEM:1566 a1(r284,l0) costs: MD1_REG:1080,1080 MD_REGS:1080,1080 ACC_REGS:1080,1080 GR_AND_MD0_REGS:360,360 GR_AND_MD1_REGS:1080,1080 GR_AND_ACC_REGS:1080,1080 M16_REGS:180,180 T_REG:180,180 PIC_FN_ADDR_REG:0,0 M16_T_REGS:180,180 LEA_REGS:180,180 GR_REGS:180,180 V1_REG:180,180 FP_REGS:720,720 MEM:1080 a2(r285,l0) costs: MD1_REG:1080,1080 MD_REGS:1080,1080 ACC_REGS:1080,1080 GR_AND_MD0_REGS:360,360 GR_AND_MD1_REGS:1080,1080 GR_AND_ACC_REGS:1080,1080 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:720,720 MEM:1080 a3(r283,l0) costs: MD1_REG:1080,1080 MD_REGS:1080,1080 ACC_REGS:1080,1080 GR_AND_MD0_REGS:360,360 GR_AND_MD1_REGS:1080,1080 GR_AND_ACC_REGS:1080,1080 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:720,720 MEM:1080 a4(r269,l0) costs: MD1_REG:1080,1080 MD_REGS:1080,1080 ACC_REGS:1080,1080 GR_AND_MD0_REGS:360,360 GR_AND_MD1_REGS:1080,1080 GR_AND_ACC_REGS:1080,1080 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:720,720 MEM:1080 a5(r281,l0) costs: MD1_REG:972,972 MD_REGS:972,972 ACC_REGS:972,972 GR_AND_MD0_REGS:324,324 GR_AND_MD1_REGS:972,972 GR_AND_ACC_REGS:972,972 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:648,648 MEM:972 a6(r264,l0) costs: MD1_REG:2538,2538 MD_REGS:2538,2538 ACC_REGS:2538,2538 GR_AND_MD0_REGS:846,846 GR_AND_MD1_REGS:2538,2538 GR_AND_ACC_REGS:2538,2538 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 MEM:2538 a7(r257,l0) costs: MD1_REG:1458,1458 MD_REGS:1458,1458 ACC_REGS:1458,1458 GR_AND_MD0_REGS:486,486 GR_AND_MD1_REGS:1458,1458 GR_AND_ACC_REGS:1458,1458 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 MEM:1458 a8(r289,l0) costs: MD1_REG:486,5946 MD_REGS:486,5946 ACC_REGS:486,5946 GR_AND_MD0_REGS:162,1982 GR_AND_MD1_REGS:486,5946 GR_AND_ACC_REGS:486,5946 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:324,3964 MEM:486 a9(r287,l0) costs: MD1_REG:1458,1458 MD_REGS:1458,1458 ACC_REGS:1458,1458 GR_AND_MD0_REGS:486,486 GR_AND_MD1_REGS:1458,1458 GR_AND_ACC_REGS:1458,1458 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:972,972 MEM:1458 a10(r267,l0) costs: MD1_REG:1026,1026 MD_REGS:1026,1026 ACC_REGS:1026,1026 GR_AND_MD0_REGS:342,342 GR_AND_MD1_REGS:1026,1026 GR_AND_ACC_REGS:1026,1026 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:684,684 MEM:1026 a11(r288,l0) costs: MD1_REG:486,5946 MD_REGS:486,5946 ACC_REGS:486,5946 GR_AND_MD0_REGS:162,1982 GR_AND_MD1_REGS:486,5946 GR_AND_ACC_REGS:486,5946 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:324,3964 MEM:486 a12(r266,l0) costs: MD1_REG:1026,1026 MD_REGS:1026,1026 ACC_REGS:1026,1026 GR_AND_MD0_REGS:342,342 GR_AND_MD1_REGS:1026,1026 GR_AND_ACC_REGS:1026,1026 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:684,684 MEM:1026 a13(r250,l0) costs: MD1_REG:486,27786 MD_REGS:486,27786 ACC_REGS:486,27786 GR_AND_MD0_REGS:162,9262 GR_AND_MD1_REGS:486,27786 GR_AND_ACC_REGS:486,27786 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:324,18524 MEM:486 a14(r262,l0) costs: MD1_REG:486,5946 MD_REGS:486,5946 ACC_REGS:486,5946 GR_AND_MD0_REGS:162,1982 GR_AND_MD1_REGS:486,5946 GR_AND_ACC_REGS:486,5946 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:324,3964 MEM:486 a15(r273,l0) costs: MD1_REG:972,972 MD_REGS:972,972 ACC_REGS:972,972 GR_AND_MD0_REGS:324,324 GR_AND_MD1_REGS:972,972 GR_AND_ACC_REGS:972,972 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:648,648 MEM:972 a16(r272,l0) costs: MD1_REG:972,972 MD_REGS:972,972 ACC_REGS:972,972 GR_AND_MD0_REGS:324,324 GR_AND_MD1_REGS:972,972 GR_AND_ACC_REGS:972,972 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:648,648 MEM:972 a17(r271,l0) costs: MD1_REG:972,972 MD_REGS:972,972 ACC_REGS:972,972 GR_AND_MD0_REGS:324,324 GR_AND_MD1_REGS:972,972 GR_AND_ACC_REGS:972,972 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:648,648 MEM:972 a18(r265,l0) costs: MD1_REG:1566,1566 MD_REGS:1566,1566 ACC_REGS:1566,1566 GR_AND_MD0_REGS:522,522 GR_AND_MD1_REGS:1566,1566 GR_AND_ACC_REGS:1566,1566 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 MEM:1566 a19(r268,l0) costs: MD1_REG:540,6000 MD_REGS:540,6000 ACC_REGS:540,6000 GR_AND_MD0_REGS:180,2000 GR_AND_MD1_REGS:540,6000 GR_AND_ACC_REGS:540,6000 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 MEM:540 a20(r270,l0) costs: MD1_REG:1080,1080 MD_REGS:1080,1080 ACC_REGS:1080,1080 GR_AND_MD0_REGS:360,360 GR_AND_MD1_REGS:1080,1080 GR_AND_ACC_REGS:1080,1080 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:720,720 MEM:1080 a21(r250,l1) costs: MD1_REG:27300,27300 MD_REGS:27300,27300 ACC_REGS:27300,27300 GR_AND_MD0_REGS:9100,9100 GR_AND_MD1_REGS:27300,27300 GR_AND_ACC_REGS:27300,27300 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:18200,18200 MEM:27300 a22(r257,l1) costs: MD1_REG:0,0 MD_REGS:0,0 ACC_REGS:0,0 GR_AND_MD0_REGS:0,0 GR_AND_MD1_REGS:0,0 GR_AND_ACC_REGS:0,0 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 MEM:0 a23(r262,l1) costs: MD1_REG:5460,5460 MD_REGS:5460,5460 ACC_REGS:5460,5460 GR_AND_MD0_REGS:1820,1820 GR_AND_MD1_REGS:5460,5460 GR_AND_ACC_REGS:5460,5460 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:3640,3640 MEM:5460 a24(r264,l1) costs: MD1_REG:0,0 MD_REGS:0,0 ACC_REGS:0,0 GR_AND_MD0_REGS:0,0 GR_AND_MD1_REGS:0,0 GR_AND_ACC_REGS:0,0 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 MEM:0 a25(r268,l1) costs: MD1_REG:5460,5460 MD_REGS:5460,5460 ACC_REGS:5460,5460 GR_AND_MD0_REGS:1820,1820 GR_AND_MD1_REGS:5460,5460 GR_AND_ACC_REGS:5460,5460 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 MEM:5460 a26(r269,l1) costs: MD1_REG:0,0 MD_REGS:0,0 ACC_REGS:0,0 GR_AND_MD0_REGS:0,0 GR_AND_MD1_REGS:0,0 GR_AND_ACC_REGS:0,0 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:0,0 MEM:0 a27(r288,l1) costs: MD1_REG:5460,5460 MD_REGS:5460,5460 ACC_REGS:5460,5460 GR_AND_MD0_REGS:1820,1820 GR_AND_MD1_REGS:5460,5460 GR_AND_ACC_REGS:5460,5460 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:3640,3640 MEM:5460 a28(r289,l1) costs: MD1_REG:5460,5460 MD_REGS:5460,5460 ACC_REGS:5460,5460 GR_AND_MD0_REGS:1820,1820 GR_AND_MD1_REGS:5460,5460 GR_AND_ACC_REGS:5460,5460 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:3640,3640 MEM:5460 a29(r275,l1) costs: MD1_REG:10920,10920 MD_REGS:10920,10920 ACC_REGS:10920,10920 GR_AND_MD0_REGS:3640,3640 GR_AND_MD1_REGS:10920,10920 GR_AND_ACC_REGS:10920,10920 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:7280,7280 MEM:10920 a30(r279,l1) costs: MD1_REG:10920,10920 MD_REGS:10920,10920 ACC_REGS:10920,10920 GR_AND_MD0_REGS:3640,3640 GR_AND_MD1_REGS:10920,10920 GR_AND_ACC_REGS:10920,10920 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:7280,7280 MEM:10920 a31(r278,l1) costs: MD1_REG:10920,10920 MD_REGS:10920,10920 ACC_REGS:10920,10920 GR_AND_MD0_REGS:3640,3640 GR_AND_MD1_REGS:10920,10920 GR_AND_ACC_REGS:10920,10920 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:7280,7280 MEM:10920 a32(r277,l1) costs: MD1_REG:10920,10920 MD_REGS:10920,10920 ACC_REGS:10920,10920 GR_AND_MD0_REGS:3640,3640 GR_AND_MD1_REGS:10920,10920 GR_AND_ACC_REGS:10920,10920 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:7280,7280 MEM:10920 Pass 1 for finding pseudo/allocno costs r289: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r288: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r287: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r285: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r284: preferred PIC_FN_ADDR_REG, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r283: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r281: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r279: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r278: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r277: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r275: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r273: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r272: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r271: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r270: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r269: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r268: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r267: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r266: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r265: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r264: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r262: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r257: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r250: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r234: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS a0(r234,l0) costs: MD1_REG:1566,1566 MD_REGS:1566,1566 ACC_REGS:1566,1566 GR_AND_MD0_REGS:522,522 GR_AND_MD1_REGS:1566,1566 GR_AND_ACC_REGS:1566,1566 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:1044,1044 MEM:1566 a1(r284,l0) costs: MD1_REG:1080,1080 MD_REGS:1080,1080 ACC_REGS:1080,1080 GR_AND_MD0_REGS:360,360 GR_AND_MD1_REGS:1080,1080 GR_AND_ACC_REGS:1080,1080 M16_REGS:180,180 T_REG:180,180 PIC_FN_ADDR_REG:0,0 M16_T_REGS:180,180 LEA_REGS:180,180 GR_REGS:180,180 V1_REG:180,180 FP_REGS:720,720 MEM:1080 a2(r285,l0) costs: MD1_REG:1080,1080 MD_REGS:1080,1080 ACC_REGS:1080,1080 GR_AND_MD0_REGS:360,360 GR_AND_MD1_REGS:1080,1080 GR_AND_ACC_REGS:1080,1080 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:720,720 MEM:1080 a3(r283,l0) costs: MD1_REG:1080,1080 MD_REGS:1080,1080 ACC_REGS:1080,1080 GR_AND_MD0_REGS:360,360 GR_AND_MD1_REGS:1080,1080 GR_AND_ACC_REGS:1080,1080 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:720,720 MEM:1080 a4(r269,l0) costs: MD1_REG:1080,1080 MD_REGS:1080,1080 ACC_REGS:1080,1080 GR_AND_MD0_REGS:360,360 GR_AND_MD1_REGS:1080,1080 GR_AND_ACC_REGS:1080,1080 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:720,720 MEM:1080 a5(r281,l0) costs: MD1_REG:972,972 MD_REGS:972,972 ACC_REGS:972,972 GR_AND_MD0_REGS:324,324 GR_AND_MD1_REGS:972,972 GR_AND_ACC_REGS:972,972 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:648,648 MEM:972 a6(r264,l0) costs: MD1_REG:2538,2538 MD_REGS:2538,2538 ACC_REGS:2538,2538 GR_AND_MD0_REGS:846,846 GR_AND_MD1_REGS:2538,2538 GR_AND_ACC_REGS:2538,2538 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 MEM:2538 a7(r257,l0) costs: MD1_REG:1458,1458 MD_REGS:1458,1458 ACC_REGS:1458,1458 GR_AND_MD0_REGS:486,486 GR_AND_MD1_REGS:1458,1458 GR_AND_ACC_REGS:1458,1458 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 MEM:1458 a8(r289,l0) costs: MD1_REG:486,5946 MD_REGS:486,5946 ACC_REGS:486,5946 GR_AND_MD0_REGS:162,1982 GR_AND_MD1_REGS:486,5946 GR_AND_ACC_REGS:486,5946 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:324,3964 MEM:486 a9(r287,l0) costs: MD1_REG:1458,1458 MD_REGS:1458,1458 ACC_REGS:1458,1458 GR_AND_MD0_REGS:486,486 GR_AND_MD1_REGS:1458,1458 GR_AND_ACC_REGS:1458,1458 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:972,972 MEM:1458 a10(r267,l0) costs: MD1_REG:1026,1026 MD_REGS:1026,1026 ACC_REGS:1026,1026 GR_AND_MD0_REGS:342,342 GR_AND_MD1_REGS:1026,1026 GR_AND_ACC_REGS:1026,1026 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:684,684 MEM:1026 a11(r288,l0) costs: MD1_REG:486,5946 MD_REGS:486,5946 ACC_REGS:486,5946 GR_AND_MD0_REGS:162,1982 GR_AND_MD1_REGS:486,5946 GR_AND_ACC_REGS:486,5946 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:324,3964 MEM:486 a12(r266,l0) costs: MD1_REG:1026,1026 MD_REGS:1026,1026 ACC_REGS:1026,1026 GR_AND_MD0_REGS:342,342 GR_AND_MD1_REGS:1026,1026 GR_AND_ACC_REGS:1026,1026 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:684,684 MEM:1026 a13(r250,l0) costs: MD1_REG:486,27786 MD_REGS:486,27786 ACC_REGS:486,27786 GR_AND_MD0_REGS:162,9262 GR_AND_MD1_REGS:486,27786 GR_AND_ACC_REGS:486,27786 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:324,18524 MEM:486 a14(r262,l0) costs: MD1_REG:486,5946 MD_REGS:486,5946 ACC_REGS:486,5946 GR_AND_MD0_REGS:162,1982 GR_AND_MD1_REGS:486,5946 GR_AND_ACC_REGS:486,5946 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:324,3964 MEM:486 a15(r273,l0) costs: MD1_REG:972,972 MD_REGS:972,972 ACC_REGS:972,972 GR_AND_MD0_REGS:324,324 GR_AND_MD1_REGS:972,972 GR_AND_ACC_REGS:972,972 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:648,648 MEM:972 a16(r272,l0) costs: MD1_REG:972,972 MD_REGS:972,972 ACC_REGS:972,972 GR_AND_MD0_REGS:324,324 GR_AND_MD1_REGS:972,972 GR_AND_ACC_REGS:972,972 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:648,648 MEM:972 a17(r271,l0) costs: MD1_REG:972,972 MD_REGS:972,972 ACC_REGS:972,972 GR_AND_MD0_REGS:324,324 GR_AND_MD1_REGS:972,972 GR_AND_ACC_REGS:972,972 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:648,648 MEM:972 a18(r265,l0) costs: MD1_REG:1566,1566 MD_REGS:1566,1566 ACC_REGS:1566,1566 GR_AND_MD0_REGS:522,522 GR_AND_MD1_REGS:1566,1566 GR_AND_ACC_REGS:1566,1566 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 MEM:1566 a19(r268,l0) costs: MD1_REG:540,6000 MD_REGS:540,6000 ACC_REGS:540,6000 GR_AND_MD0_REGS:180,2000 GR_AND_MD1_REGS:540,6000 GR_AND_ACC_REGS:540,6000 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 MEM:540 a20(r270,l0) costs: MD1_REG:1080,1080 MD_REGS:1080,1080 ACC_REGS:1080,1080 GR_AND_MD0_REGS:360,360 GR_AND_MD1_REGS:1080,1080 GR_AND_ACC_REGS:1080,1080 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:720,720 MEM:1080 a21(r250,l1) costs: MD1_REG:27300,27300 MD_REGS:27300,27300 ACC_REGS:27300,27300 GR_AND_MD0_REGS:9100,9100 GR_AND_MD1_REGS:27300,27300 GR_AND_ACC_REGS:27300,27300 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:18200,18200 MEM:27300 a22(r257,l1) costs: MD1_REG:0,0 MD_REGS:0,0 ACC_REGS:0,0 GR_AND_MD0_REGS:0,0 GR_AND_MD1_REGS:0,0 GR_AND_ACC_REGS:0,0 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 MEM:0 a23(r262,l1) costs: MD1_REG:5460,5460 MD_REGS:5460,5460 ACC_REGS:5460,5460 GR_AND_MD0_REGS:1820,1820 GR_AND_MD1_REGS:5460,5460 GR_AND_ACC_REGS:5460,5460 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:3640,3640 MEM:5460 a24(r264,l1) costs: MD1_REG:0,0 MD_REGS:0,0 ACC_REGS:0,0 GR_AND_MD0_REGS:0,0 GR_AND_MD1_REGS:0,0 GR_AND_ACC_REGS:0,0 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 MEM:0 a25(r268,l1) costs: MD1_REG:5460,5460 MD_REGS:5460,5460 ACC_REGS:5460,5460 GR_AND_MD0_REGS:1820,1820 GR_AND_MD1_REGS:5460,5460 GR_AND_ACC_REGS:5460,5460 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 MEM:5460 a26(r269,l1) costs: MD1_REG:0,0 MD_REGS:0,0 ACC_REGS:0,0 GR_AND_MD0_REGS:0,0 GR_AND_MD1_REGS:0,0 GR_AND_ACC_REGS:0,0 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:0,0 MEM:0 a27(r288,l1) costs: MD1_REG:5460,5460 MD_REGS:5460,5460 ACC_REGS:5460,5460 GR_AND_MD0_REGS:1820,1820 GR_AND_MD1_REGS:5460,5460 GR_AND_ACC_REGS:5460,5460 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:3640,3640 MEM:5460 a28(r289,l1) costs: MD1_REG:5460,5460 MD_REGS:5460,5460 ACC_REGS:5460,5460 GR_AND_MD0_REGS:1820,1820 GR_AND_MD1_REGS:5460,5460 GR_AND_ACC_REGS:5460,5460 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:3640,3640 MEM:5460 a29(r275,l1) costs: MD1_REG:10920,10920 MD_REGS:10920,10920 ACC_REGS:10920,10920 GR_AND_MD0_REGS:3640,3640 GR_AND_MD1_REGS:10920,10920 GR_AND_ACC_REGS:10920,10920 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:7280,7280 MEM:10920 a30(r279,l1) costs: MD1_REG:10920,10920 MD_REGS:10920,10920 ACC_REGS:10920,10920 GR_AND_MD0_REGS:3640,3640 GR_AND_MD1_REGS:10920,10920 GR_AND_ACC_REGS:10920,10920 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:7280,7280 MEM:10920 a31(r278,l1) costs: MD1_REG:10920,10920 MD_REGS:10920,10920 ACC_REGS:10920,10920 GR_AND_MD0_REGS:3640,3640 GR_AND_MD1_REGS:10920,10920 GR_AND_ACC_REGS:10920,10920 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:7280,7280 MEM:10920 a32(r277,l1) costs: MD1_REG:10920,10920 MD_REGS:10920,10920 ACC_REGS:10920,10920 GR_AND_MD0_REGS:3640,3640 GR_AND_MD1_REGS:10920,10920 GR_AND_ACC_REGS:10920,10920 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:7280,7280 MEM:10920 Insn 94(l0): point = 0 Insn 91(l0): point = 2 Insn 86(l0): point = 4 Insn 85(l0): point = 6 Insn 82(l0): point = 8 Insn 109(l0): point = 10 Insn 84(l0): point = 12 Insn 80(l0): point = 14 Insn 83(l0): point = 16 Insn 79(l0): point = 18 Insn 76(l0): point = 21 Insn 74(l0): point = 23 Insn 64(l0): point = 26 Insn 62(l0): point = 28 Insn 47(l0): point = 30 Insn 58(l0): point = 32 Insn 57(l0): point = 34 Insn 103(l0): point = 36 Insn 56(l0): point = 38 Insn 55(l0): point = 40 Insn 54(l0): point = 42 Insn 52(l0): point = 45 Insn 48(l0): point = 47 Insn 45(l0): point = 49 Insn 44(l0): point = 51 Insn 43(l0): point = 53 Insn 42(l0): point = 55 Insn 51(l0): point = 57 Insn 41(l0): point = 59 Insn 40(l0): point = 61 Insn 71(l1): point = 64 Insn 68(l1): point = 66 Insn 67(l1): point = 68 Insn 69(l1): point = 70 Insn 63(l1): point = 72 Insn 66(l1): point = 74 Insn 65(l1): point = 76 a0(r234): [45..47] [3..21] a1(r284): [7..14] a2(r285): [9..10] a3(r283): [15..18] a4(r269): [19..49] a5(r281): [22..23] a6(r264): [24..61] a7(r257): [24..42] a8(r289): [26..26] a9(r287): [27..36] a10(r267): [27..53] a11(r288): [26..28] a12(r266): [29..55] a13(r250): [26..30] a14(r262): [26..32] a15(r273): [33..34] a16(r272): [35..38] a17(r271): [39..40] a18(r265): [43..59] a19(r268): [26..51] a20(r270): [46..57] a21(r250): [64..78] a22(r257): [64..78] a23(r262): [64..78] a24(r264): [64..78] a25(r268): [64..78] a26(r269): [64..78] a27(r288): [64..78] a28(r289): [64..78] a29(r275): [67..72] a30(r279): [67..68] a31(r278): [69..74] a32(r277): [75..76] Moving ranges of a28r289 to a8r289: [64..78] Moving ranges of a27r288 to a11r288: [64..78] Rebuilding regno allocno list for 279 Rebuilding regno allocno list for 278 Rebuilding regno allocno list for 277 Rebuilding regno allocno list for 275 Moving ranges of a26r269 to a4r269: [64..78] Moving ranges of a25r268 to a19r268: [64..78] Moving ranges of a24r264 to a6r264: [64..78] Moving ranges of a23r262 to a14r262: [64..78] Moving ranges of a22r257 to a7r257: [64..78] Moving ranges of a21r250 to a13r250: [64..78] Compressing live ranges: from 79 to 28 - 35% Ranges after the compression: a0(r234): [20..21] [0..5] a1(r284): [0..1] a2(r285): [0..1] a3(r283): [2..3] a4(r269): [22..27] [4..21] a5(r281): [6..7] a6(r264): [22..27] [8..21] a7(r257): [22..27] [8..19] a8(r289): [22..27] [9..9] a9(r287): [10..17] a10(r267): [10..21] a11(r288): [22..27] [9..11] a12(r266): [12..21] a13(r250): [22..27] [9..13] a14(r262): [22..27] [9..13] a15(r273): [14..15] a16(r272): [16..17] a17(r271): [18..19] a18(r265): [20..21] a19(r268): [22..27] [9..21] a20(r270): [20..21] a29(r275): [22..25] a30(r279): [22..23] a31(r278): [24..25] a32(r277): [26..27] +++Allocating 200 bytes for conflict table (uncompressed size 264) ;; a0(r234,l0) conflicts: a1(r284,l0) a2(r285,l0) a3(r283,l0) a4(r269,l0) a6(r264,l0) a19(r268,l0) a10(r267,l0) a12(r266,l0) a18(r265,l0) a20(r270,l0) ;; total conflict hard regs: 2 4-6 31 64 65 ;; conflict hard regs: 2 4-6 31 64 65 ;; a1(r284,l0) conflicts: a2(r285,l0) a0(r234,l0) ;; total conflict hard regs: 4-6 31 ;; conflict hard regs: 4-6 31 ;; a2(r285,l0) conflicts: a1(r284,l0) a0(r234,l0) ;; total conflict hard regs: 5 6 ;; conflict hard regs: 5 6 ;; a3(r283,l0) conflicts: a0(r234,l0) ;; total conflict hard regs: 5 ;; conflict hard regs: 5 ;; a4(r269,l0) conflicts: a0(r234,l0) a5(r281,l0) a6(r264,l0) a7(r257,l0) a8(r289,l0) a11(r288,l0) a13(r250,l0) a14(r262,l0) a19(r268,l0) a9(r287,l0) a10(r267,l0) a12(r266,l0) a15(r273,l0) a16(r272,l0) a17(r271,l0) a18(r265,l0) a20(r270,l0) a30(r279,l0) a29(r275,l0) a31(r278,l0) a32(r277,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a5(r281,l0) conflicts: a4(r269,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a6(r264,l0) conflicts: a0(r234,l0) a4(r269,l0) a7(r257,l0) a8(r289,l0) a11(r288,l0) a13(r250,l0) a14(r262,l0) a19(r268,l0) a9(r287,l0) a10(r267,l0) a12(r266,l0) a15(r273,l0) a16(r272,l0) a17(r271,l0) a18(r265,l0) a20(r270,l0) a30(r279,l0) a29(r275,l0) a31(r278,l0) a32(r277,l0) ;; total conflict hard regs: 5-9 ;; conflict hard regs: 5-9 ;; a7(r257,l0) conflicts: a4(r269,l0) a6(r264,l0) a8(r289,l0) a11(r288,l0) a13(r250,l0) a14(r262,l0) a19(r268,l0) a9(r287,l0) a10(r267,l0) a12(r266,l0) a15(r273,l0) a16(r272,l0) a17(r271,l0) a30(r279,l0) a29(r275,l0) a31(r278,l0) a32(r277,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a8(r289,l0) conflicts: a4(r269,l0) a6(r264,l0) a7(r257,l0) a11(r288,l0) a13(r250,l0) a14(r262,l0) a19(r268,l0) a30(r279,l0) a29(r275,l0) a31(r278,l0) a32(r277,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a9(r287,l0) conflicts: a4(r269,l0) a6(r264,l0) a7(r257,l0) a11(r288,l0) a13(r250,l0) a14(r262,l0) a19(r268,l0) a10(r267,l0) a12(r266,l0) a15(r273,l0) a16(r272,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a10(r267,l0) conflicts: a0(r234,l0) a4(r269,l0) a6(r264,l0) a7(r257,l0) a11(r288,l0) a13(r250,l0) a14(r262,l0) a19(r268,l0) a9(r287,l0) a12(r266,l0) a15(r273,l0) a16(r272,l0) a17(r271,l0) a18(r265,l0) a20(r270,l0) ;; total conflict hard regs: 8 9 ;; conflict hard regs: 8 9 ;; a11(r288,l0) conflicts: a4(r269,l0) a6(r264,l0) a7(r257,l0) a8(r289,l0) a13(r250,l0) a14(r262,l0) a19(r268,l0) a9(r287,l0) a10(r267,l0) a30(r279,l0) a29(r275,l0) a31(r278,l0) a32(r277,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a12(r266,l0) conflicts: a0(r234,l0) a4(r269,l0) a6(r264,l0) a7(r257,l0) a13(r250,l0) a14(r262,l0) a19(r268,l0) a9(r287,l0) a10(r267,l0) a15(r273,l0) a16(r272,l0) a17(r271,l0) a18(r265,l0) a20(r270,l0) ;; total conflict hard regs: 7-9 ;; conflict hard regs: 7-9 ;; a13(r250,l0) conflicts: a4(r269,l0) a6(r264,l0) a7(r257,l0) a8(r289,l0) a11(r288,l0) a14(r262,l0) a19(r268,l0) a9(r287,l0) a10(r267,l0) a12(r266,l0) a30(r279,l0) a29(r275,l0) a31(r278,l0) a32(r277,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a14(r262,l0) conflicts: a4(r269,l0) a6(r264,l0) a7(r257,l0) a8(r289,l0) a11(r288,l0) a13(r250,l0) a19(r268,l0) a9(r287,l0) a10(r267,l0) a12(r266,l0) a30(r279,l0) a29(r275,l0) a31(r278,l0) a32(r277,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a15(r273,l0) conflicts: a4(r269,l0) a6(r264,l0) a7(r257,l0) a19(r268,l0) a9(r287,l0) a10(r267,l0) a12(r266,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a16(r272,l0) conflicts: a4(r269,l0) a6(r264,l0) a7(r257,l0) a19(r268,l0) a9(r287,l0) a10(r267,l0) a12(r266,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a17(r271,l0) conflicts: a4(r269,l0) a6(r264,l0) a7(r257,l0) a19(r268,l0) a10(r267,l0) a12(r266,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a18(r265,l0) conflicts: a0(r234,l0) a4(r269,l0) a6(r264,l0) a19(r268,l0) a10(r267,l0) a12(r266,l0) a20(r270,l0) ;; total conflict hard regs: 6-9 ;; conflict hard regs: 6-9 ;; a19(r268,l0) conflicts: a0(r234,l0) a4(r269,l0) a6(r264,l0) a7(r257,l0) a8(r289,l0) a11(r288,l0) a13(r250,l0) a14(r262,l0) a9(r287,l0) a10(r267,l0) a12(r266,l0) a15(r273,l0) a16(r272,l0) a17(r271,l0) a18(r265,l0) a20(r270,l0) a30(r279,l0) a29(r275,l0) a31(r278,l0) a32(r277,l0) ;; total conflict hard regs: 9 ;; conflict hard regs: 9 ;; a20(r270,l0) conflicts: a0(r234,l0) a4(r269,l0) a6(r264,l0) a19(r268,l0) a10(r267,l0) a12(r266,l0) a18(r265,l0) ;; total conflict hard regs: 6-9 ;; conflict hard regs: 6-9 ;; a29(r275,l0) conflicts: a4(r269,l0) a6(r264,l0) a7(r257,l0) a8(r289,l0) a11(r288,l0) a13(r250,l0) a14(r262,l0) a19(r268,l0) a30(r279,l0) a31(r278,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a30(r279,l0) conflicts: a4(r269,l0) a6(r264,l0) a7(r257,l0) a8(r289,l0) a11(r288,l0) a13(r250,l0) a14(r262,l0) a19(r268,l0) a29(r275,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a31(r278,l0) conflicts: a4(r269,l0) a6(r264,l0) a7(r257,l0) a8(r289,l0) a11(r288,l0) a13(r250,l0) a14(r262,l0) a19(r268,l0) a29(r275,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a32(r277,l0) conflicts: a4(r269,l0) a6(r264,l0) a7(r257,l0) a8(r289,l0) a11(r288,l0) a13(r250,l0) a14(r262,l0) a19(r268,l0) ;; total conflict hard regs: ;; conflict hard regs: cp0:a5(r281)<->a7(r257)@10:shuffle cp1:a5(r281)<->a6(r264)@10:shuffle cp2:a0(r234)<->a5(r281)@10:shuffle cp3:a30(r279)<->a31(r278)@113:shuffle cp4:a7(r257)<->a18(r265)@10:shuffle cp5:a16(r272)<->a17(r271)@10:shuffle cp6:a15(r273)<->a16(r272)@10:shuffle cp7:a14(r262)<->a15(r273)@10:shuffle cp8:a11(r288)<->a12(r266)@10:shuffle cp9:a8(r289)<->a10(r267)@10:shuffle cp10:a8(r289)<->a9(r287)@10:shuffle regions=2, blocks=7, points=28 allocnos=33 (big 0), copies=11, conflicts=2, ranges=34 **** Allocnos coloring: Loop 0 (parent -1, header bb0, depth 0) bbs: 6 5 4 3 2 all: 0r234 1r284 2r285 3r283 4r269 5r281 6r264 7r257 8r289 9r287 10r267 11r288 12r266 13r250 14r262 15r273 16r272 17r271 18r265 19r268 20r270 29r275 30r279 31r278 32r277 modified regnos: 234 250 257 262 264 265 266 267 268 269 270 271 272 273 275 277 278 279 281 283 284 285 287 288 289 border: Pressure: GR_AND_ACC_REGS=10 Reg 234 of GR_AND_ACC_REGS has 7 regs less Reg 284 of GR_AND_ACC_REGS has 5 regs less Reg 285 of GR_AND_ACC_REGS has 3 regs less Reg 283 of GR_AND_ACC_REGS has 2 regs less Reg 269 of GR_AND_ACC_REGS has 1 regs less Reg 281 of GR_AND_ACC_REGS has 1 regs less Reg 264 of GR_AND_ACC_REGS has 6 regs less Reg 257 of GR_AND_ACC_REGS has 1 regs less Reg 289 of GR_AND_ACC_REGS has 1 regs less Reg 287 of GR_AND_ACC_REGS has 1 regs less Reg 267 of GR_AND_ACC_REGS has 3 regs less Reg 288 of GR_AND_ACC_REGS has 1 regs less Reg 266 of GR_AND_ACC_REGS has 4 regs less Reg 250 of GR_AND_ACC_REGS has 1 regs less Reg 262 of GR_AND_ACC_REGS has 1 regs less Reg 273 of GR_AND_ACC_REGS has 1 regs less Reg 272 of GR_AND_ACC_REGS has 1 regs less Reg 271 of GR_AND_ACC_REGS has 1 regs less Reg 265 of GR_AND_ACC_REGS has 5 regs less Reg 268 of GR_AND_ACC_REGS has 2 regs less Reg 270 of GR_AND_ACC_REGS has 5 regs less Reg 275 of GR_AND_ACC_REGS has 1 regs less Reg 279 of GR_AND_ACC_REGS has 1 regs less Reg 278 of GR_AND_ACC_REGS has 1 regs less Reg 277 of GR_AND_ACC_REGS has 1 regs less Pushing a17(r271,l0) Pushing a16(r272,l0) Pushing a15(r273,l0) Pushing a5(r281,l0) Pushing a4(r269,l0) Pushing a9(r287,l0) Pushing a7(r257,l0) Pushing a14(r262,l0) Pushing a11(r288,l0) Pushing a8(r289,l0) Pushing a32(r277,l0) Pushing a31(r278,l0) Pushing a30(r279,l0) Pushing a29(r275,l0) Pushing a13(r250,l0) Pushing a3(r283,l0) Pushing a19(r268,l0) Pushing a10(r267,l0) Pushing a2(r285,l0) Pushing a12(r266,l0) Pushing a20(r270,l0) Pushing a1(r284,l0) Pushing a18(r265,l0) Pushing a6(r264,l0) Pushing a0(r234,l0) Popping a0(r234,l0) -- assign reg 16 Popping a6(r264,l0) -- assign reg 4 Popping a18(r265,l0) -- assign reg 5 Popping a1(r284,l0) -- assign reg 25 Popping a20(r270,l0) -- assign reg 2 Popping a12(r266,l0) -- assign reg 6 Popping a2(r285,l0) -- assign reg 4 Popping a10(r267,l0) -- assign reg 7 Popping a19(r268,l0) -- assign reg 8 Popping a3(r283,l0) -- assign reg 2 Popping a13(r250,l0) -- assign reg 2 Popping a29(r275,l0) -- assign reg 3 Popping a30(r279,l0) -- assign reg 10 Popping a31(r278,l0) -- assign reg 10 Popping a32(r277,l0) -- assign reg 3 Popping a8(r289,l0) -- assign reg 7 Popping a11(r288,l0) -- assign reg 6 Popping a14(r262,l0) -- assign reg 11 Popping a7(r257,l0) -- assign reg 5 Popping a9(r287,l0) -- assign reg 3 Popping a4(r269,l0) -- assign reg 9 Popping a5(r281,l0) -- assign reg 5 Popping a15(r273,l0) -- assign reg 11 Popping a16(r272,l0) -- assign reg 11 Popping a17(r271,l0) -- assign reg 11 Disposition: 0:r234 l0 16 13:r250 l0 2 7:r257 l0 5 14:r262 l0 11 6:r264 l0 4 18:r265 l0 5 12:r266 l0 6 10:r267 l0 7 19:r268 l0 8 4:r269 l0 9 20:r270 l0 2 17:r271 l0 11 16:r272 l0 11 15:r273 l0 11 29:r275 l0 3 32:r277 l0 3 31:r278 l0 10 30:r279 l0 10 5:r281 l0 5 3:r283 l0 2 1:r284 l0 25 2:r285 l0 4 9:r287 l0 3 11:r288 l0 6 8:r289 l0 7 New iteration of spill/restore move +++Costs: overall -6546, reg -6546, mem 0, ld 0, st 0, move 0 +++ move loops 0, new jumps 0 insn=40, live_throughout: 5, 6, 7, 8, 9, 28, 29, 79, dead_or_set: 4, 264 insn=41, live_throughout: 6, 7, 8, 9, 28, 29, 79, 264, dead_or_set: 5, 265 insn=51, live_throughout: 6, 7, 8, 9, 28, 29, 79, 264, 265, dead_or_set: 270 insn=42, live_throughout: 7, 8, 9, 28, 29, 79, 264, 265, 270, dead_or_set: 6, 266 insn=43, live_throughout: 8, 9, 28, 29, 79, 264, 265, 266, 270, dead_or_set: 7, 267 insn=44, live_throughout: 9, 28, 29, 79, 264, 265, 266, 267, 270, dead_or_set: 8, 268 insn=45, live_throughout: 28, 29, 79, 264, 265, 266, 267, 268, 270, dead_or_set: 9, 269 insn=48, live_throughout: 28, 29, 79, 264, 265, 266, 267, 268, 269, 270, dead_or_set: 234 insn=52, live_throughout: 28, 29, 79, 234, 264, 265, 266, 267, 268, 269, dead_or_set: 270 insn=54, live_throughout: 28, 29, 79, 264, 266, 267, 268, 269, dead_or_set: 257, 265 insn=55, live_throughout: 28, 29, 79, 257, 264, 266, 267, 268, 269, dead_or_set: 271 insn=56, live_throughout: 28, 29, 79, 257, 264, 266, 267, 268, 269, dead_or_set: 271, 272 insn=103, live_throughout: 28, 29, 79, 257, 264, 266, 267, 268, 269, 272, dead_or_set: 287 insn=57, live_throughout: 28, 29, 79, 257, 264, 266, 267, 268, 269, 287, dead_or_set: 272, 273 insn=58, live_throughout: 28, 29, 79, 257, 264, 266, 267, 268, 269, 287, dead_or_set: 262, 273 insn=47, live_throughout: 28, 29, 79, 257, 262, 264, 266, 267, 268, 269, 287, dead_or_set: 250 insn=62, live_throughout: 28, 29, 79, 250, 257, 262, 264, 267, 268, 269, 287, dead_or_set: 266, 288 insn=64, live_throughout: 28, 29, 79, 250, 257, 262, 264, 268, 269, 288, dead_or_set: 267, 287, 289 insn=70, live_throughout: 28, 29, 79, 250, 257, 262, 264, 268, 269, 288, 289, dead_or_set: insn=65, live_throughout: 28, 29, 79, 250, 257, 262, 264, 268, 269, 288, 289, dead_or_set: 277 insn=66, live_throughout: 28, 29, 79, 250, 257, 262, 264, 268, 269, 288, 289, dead_or_set: 277, 278 insn=63, live_throughout: 28, 29, 79, 250, 257, 262, 264, 268, 269, 278, 288, 289, dead_or_set: 275 insn=69, live_throughout: 28, 29, 79, 257, 262, 264, 268, 269, 275, 278, 288, 289, dead_or_set: 250 insn=67, live_throughout: 28, 29, 79, 250, 257, 262, 264, 268, 269, 275, 288, 289, dead_or_set: 278, 279 insn=68, live_throughout: 28, 29, 79, 250, 257, 262, 264, 268, 269, 288, 289, dead_or_set: 275, 279 insn=71, live_throughout: 28, 29, 79, 250, 257, 262, 264, 268, 269, 288, 289, dead_or_set: insn=74, live_throughout: 28, 29, 79, 269, dead_or_set: 257, 264, 281 insn=76, live_throughout: 28, 29, 79, 269, dead_or_set: 234, 281 insn=77, live_throughout: 28, 29, 79, 234, 269, dead_or_set: insn=79, live_throughout: 28, 29, 79, 234, dead_or_set: 269, 283 insn=83, live_throughout: 28, 29, 79, 234, 283, dead_or_set: 5 insn=80, live_throughout: 5, 28, 29, 79, 234, dead_or_set: 283, 284 insn=84, live_throughout: 5, 28, 29, 79, 234, 284, dead_or_set: 6 insn=109, live_throughout: 5, 6, 28, 29, 79, 234, 284, dead_or_set: 285 insn=82, live_throughout: 5, 6, 28, 29, 79, 234, 284, dead_or_set: 4, 285 insn=85, live_throughout: 28, 29, 79, 234, dead_or_set: 2, 4, 5, 6, 31, 284 insn=86, live_throughout: 28, 29, 31, 234, dead_or_set: insn=91, live_throughout: 28, 29, 31, 79, dead_or_set: 2, 234 insn=94, live_throughout: 2, 28, 29, 31, 79, dead_or_set: init_insns for 279: (insn_list:REG_DEP_TRUE 68 (nil)) init_insns for 285: (insn_list:REG_DEP_TRUE 109 (nil)) changing reg in insn 76 changing reg in insn 48 changing reg in insn 91 changing reg in insn 69 changing reg in insn 47 changing reg in insn 65 changing reg in insn 63 changing reg in insn 71 changing reg in insn 69 changing reg in insn 54 changing reg in insn 58 changing reg in insn 71 changing reg in insn 40 changing reg in insn 103 changing reg in insn 41 changing reg in insn 42 changing reg in insn 62 changing reg in insn 43 changing reg in insn 64 changing reg in insn 44 changing reg in insn 45 changing reg in insn 79 changing reg in insn 51 changing reg in insn 52 changing reg in insn 55 changing reg in insn 56 changing reg in insn 56 changing reg in insn 57 changing reg in insn 57 changing reg in insn 58 changing reg in insn 63 changing reg in insn 68 changing reg in insn 67 changing reg in insn 65 changing reg in insn 66 changing reg in insn 66 changing reg in insn 67 changing reg in insn 67 changing reg in insn 68 changing reg in insn 74 changing reg in insn 76 changing reg in insn 79 changing reg in insn 80 changing reg in insn 80 changing reg in insn 85 changing reg in insn 109 changing reg in insn 82 changing reg in insn 103 changing reg in insn 64 changing reg in insn 62 changing reg in insn 62 changing reg in insn 63 changing reg in insn 64 changing reg in insn 65 Spilling for insn 68. Reloads for insn # 68 Reload 0: GR_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum = 0), optional, can't combine, secondary_reload_p Reload 1: reload_out (SI) = (mem:SI (reg:DI 3 $3 [275]) [2 MEM[base: D.2063_52, offset: 0B]+0 S4 A32]) NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional reload_out_reg: (mem:SI (reg:DI 3 $3 [275]) [2 MEM[base: D.2063_52, offset: 0B]+0 S4 A32]) secondary_out_reload = 0 deleting insn with uid = 40. deleting insn with uid = 41. deleting insn with uid = 42. deleting insn with uid = 43. deleting insn with uid = 44. deleting insn with uid = 45. try_optimize_cfg iteration 1 starting the processing of deferred insns ending the processing of deferred insns rescanning insn with uid = 85. deleting insn with uid = 85. starting the processing of deferred insns ending the processing of deferred insns df_analyze called df_worklist_dataflow_doublequeue:n_basic_blocks 7 n_edges 8 count 8 ( 1.1) df_worklist_dataflow_doublequeue:n_basic_blocks 7 n_edges 8 count 8 ( 1.1) (note 39 0 49 NOTE_INSN_DELETED) (note 49 39 46 2 [bb 2] NOTE_INSN_BASIC_BLOCK) (note 46 49 51 2 NOTE_INSN_FUNCTION_BEG) (insn 51 46 48 2 (set (reg:SI 2 $2 [270]) (gt:SI (reg:SI 4 $4 [orig:264 start ] [264]) (reg:SI 5 $5 [orig:265 end ] [265]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:38 460 {*sgt_sisi} (nil)) (insn 48 51 52 2 (set (reg/v:DI 16 $16 [orig:234 count+-4 ] [234]) (const_int 0 [0])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:35 276 {*movdi_64bit} (expr_list:REG_EQUAL (const_int 0 [0]) (nil))) (jump_insn 52 48 53 2 (set (pc) (if_then_else (ne (reg:SI 2 $2 [270]) (const_int 0 [0])) (label_ref:DI 77) (pc))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:38 426 {*branch_equalitysi} (expr_list:REG_BR_PROB (const_int 900 [0x384]) (nil)) -> 77) (note 53 52 54 3 [bb 3] NOTE_INSN_BASIC_BLOCK) (insn 54 53 55 3 (set (reg:DI 5 $5 [orig:257 D.2064+-4 ] [257]) (sign_extend:DI (reg:SI 5 $5 [orig:265 end ] [265]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 202 {extendsidi2} (nil)) (insn 55 54 56 3 (set (reg:SI 11 $11 [271]) (minus:SI (reg:SI 5 $5 [orig:257 D.2064 ] [257]) (reg:SI 4 $4 [orig:264 start ] [264]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 23 {subsi3} (nil)) (insn 56 55 103 3 (set (reg:DI 11 $11 [272]) (zero_extend:DI (reg:SI 11 $11 [271]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 181 {*zero_extendsidi2} (nil)) (insn 103 56 57 3 (set (reg:DI 3 $3 [orig:287 D.2057 ] [287]) (ashift:DI (reg/v:DI 4 $4 [orig:264 start+-4 ] [264]) (const_int 2 [0x2]))) 405 {*ashldi3} (nil)) (insn 57 103 58 3 (set (reg:DI 11 $11 [273]) (plus:DI (reg:DI 11 $11 [272]) (const_int 1 [0x1]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 11 {*adddi3} (nil)) (insn 58 57 47 3 (set (reg:DI 11 $11 [orig:262 D.2069 ] [262]) (ashift:DI (reg:DI 11 $11 [273]) (const_int 2 [0x2]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 405 {*ashldi3} (nil)) (insn 47 58 62 3 (set (reg:DI 2 $2 [orig:250 ivtmp.16 ] [250]) (const_int 0 [0])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 276 {*movdi_64bit} (expr_list:REG_EQUAL (const_int 0 [0]) (nil))) (insn 62 47 64 3 (set (reg:DI 6 $6 [288]) (plus:DI (reg/v/f:DI 6 $6 [orig:266 a ] [266]) (reg:DI 3 $3 [orig:287 D.2057 ] [287]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 11 {*adddi3} (nil)) (insn 64 62 70 3 (set (reg:DI 7 $7 [289]) (plus:DI (reg/v/f:DI 7 $7 [orig:267 b ] [267]) (reg:DI 3 $3 [orig:287 D.2057 ] [287]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 11 {*adddi3} (nil)) (code_label 70 64 59 4 3 "" [1 uses]) (note 59 70 65 4 [bb 4] NOTE_INSN_BASIC_BLOCK) (insn 65 59 66 4 (set (reg:DI 3 $3 [277]) (plus:DI (reg:DI 7 $7 [289]) (reg:DI 2 $2 [orig:250 ivtmp.16 ] [250]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 11 {*adddi3} (nil)) (insn 66 65 63 4 (set (reg:SI 10 $10 [orig:278 MEM[base: D.2059_48, offset: 0B] ] [278]) (mem:SI (reg:DI 3 $3 [277]) [2 MEM[base: D.2059_48, offset: 0B]+0 S4 A32])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:40 278 {*movsi_internal} (nil)) (insn 63 66 69 4 (set (reg:DI 3 $3 [275]) (plus:DI (reg:DI 6 $6 [288]) (reg:DI 2 $2 [orig:250 ivtmp.16 ] [250]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 11 {*adddi3} (nil)) (insn 69 63 67 4 (set (reg:DI 2 $2 [orig:250 ivtmp.16 ] [250]) (plus:DI (reg:DI 2 $2 [orig:250 ivtmp.16 ] [250]) (const_int 4 [0x4]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:40 11 {*adddi3} (nil)) (insn 67 69 68 4 (set (reg:SI 10 $10 [279]) (plus:SI (reg:SI 10 $10 [orig:278 MEM[base: D.2059_48, offset: 0B] ] [278]) (reg:SI 8 $8 [orig:268 c ] [268]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:40 10 {*addsi3} (expr_list:REG_EQUIV (mem:SI (reg:DI 3 $3 [275]) [2 MEM[base: D.2063_52, offset: 0B]+0 S4 A32]) (nil))) (insn 68 67 71 4 (set (mem:SI (reg:DI 3 $3 [275]) [2 MEM[base: D.2063_52, offset: 0B]+0 S4 A32]) (reg:SI 10 $10 [279])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:40 278 {*movsi_internal} (nil)) (jump_insn 71 68 72 4 (set (pc) (if_then_else (ne (reg:DI 2 $2 [orig:250 ivtmp.16 ] [250]) (reg:DI 11 $11 [orig:262 D.2069 ] [262])) (label_ref:DI 70) (pc))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:38 427 {*branch_equalitydi} (expr_list:REG_BR_PROB (const_int 9100 [0x238c]) (nil)) -> 70) (note 72 71 73 5 [bb 5] NOTE_INSN_BASIC_BLOCK) (note 73 72 75 5 NOTE_INSN_DELETED) (note 75 73 74 5 NOTE_INSN_DELETED) (insn 74 75 76 5 (set (reg:SI 5 $5 [281]) (minus:SI (reg:SI 5 $5 [orig:257 D.2064 ] [257]) (reg:SI 4 $4 [orig:264 start ] [264]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:33 23 {subsi3} (nil)) (insn 76 74 77 5 (set (reg/v:DI 16 $16 [orig:234 count+-4 ] [234]) (sign_extend:DI (plus:SI (reg:SI 5 $5 [281]) (const_int 1 [0x1])))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:38 14 {*addsi3_extended} (nil)) (code_label 77 76 78 6 2 "" [1 uses]) (note 78 77 79 6 [bb 6] NOTE_INSN_BASIC_BLOCK) (insn 79 78 83 6 (set (reg/f:DI 2 $2 [orig:283 sp_20(D)->s ] [283]) (mem/s/f:DI (plus:DI (reg/v/f:DI 9 $9 [orig:269 sp ] [269]) (const_int 16 [0x10])) [4 sp_20(D)->s+0 S8 A64])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:43 276 {*movdi_64bit} (nil)) (insn 83 79 80 6 (set (reg:DI 5 $5) (symbol_ref:DI ("exit") [flags 0x41] )) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:43 263 {*got_dispdi} (nil)) (insn 80 83 84 6 (set (reg/f:DI 25 $25 [orig:284 D.2020_21->vp ] [284]) (mem/s/f:DI (plus:DI (reg/f:DI 2 $2 [orig:283 sp_20(D)->s ] [283]) (const_int 8 [0x8])) [4 D.2020_21->vp+0 S8 A64])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:43 276 {*movdi_64bit} (nil)) (insn 84 80 109 6 (set (reg:DI 6 $6) (symbol_ref:DI ("M_var") [flags 0x2] )) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:43 263 {*got_dispdi} (nil)) (insn 109 84 82 6 (set (reg/f:DI 4 $4 [285]) (high:DI (symbol_ref/f:DI ("*.LC0") [flags 0x2] ))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:43 265 {*got_pagedi} (expr_list:REG_EQUIV (high:DI (symbol_ref/f:DI ("*.LC0") [flags 0x2] )) (nil))) (insn 82 109 85 6 (set (reg:DI 4 $4) (lo_sum:DI (reg/f:DI 4 $4 [285]) (symbol_ref/f:DI ("*.LC0") [flags 0x2] ))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:43 269 {*lowdi} (expr_list:REG_EQUAL (symbol_ref/f:DI ("*.LC0") [flags 0x2] ) (nil))) (call_insn 85 82 86 6 (parallel [ (set (reg:DI 2 $2) (call (mem:SI (reg/f:DI 25 $25 [orig:284 D.2020_21->vp ] [284]) [0 S4 A32]) (const_int 0 [0]))) (clobber (reg:SI 31 $31)) ]) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:43 570 {call_value_internal} (nil) (expr_list:REG_DEP_TRUE (use (reg:DI 79 $fakec)) (expr_list:REG_DEP_TRUE (use (reg:DI 6 $6)) (expr_list:REG_DEP_TRUE (use (reg:DI 5 $5)) (expr_list:REG_DEP_TRUE (use (reg:DI 4 $4)) (nil)))))) (insn 86 85 91 6 (set (reg:SI 79 $fakec) (unspec:SI [ (reg:SI 79 $fakec) ] UNSPEC_UPDATE_GOT_VERSION)) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:43 562 {update_got_version} (nil)) (insn 91 86 94 6 (set (reg/i:DI 2 $2) (reg/v:DI 16 $16 [orig:234 count+-4 ] [234])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:45 276 {*movdi_64bit} (nil)) (insn 94 91 108 6 (use (reg/i:DI 2 $2)) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:45 -1 (nil)) (note 108 94 110 NOTE_INSN_DELETED) (note 110 108 0 NOTE_INSN_DELETED) ;; Function g (g) starting the processing of deferred insns ending the processing of deferred insns df_analyze called scanning new insn with uid = 35. verify found no changes in insn with uid = 35. deleting insn with uid = 12. Building IRA IR starting the processing of deferred insns ending the processing of deferred insns df_analyze called df_worklist_dataflow_doublequeue:n_basic_blocks 5 n_edges 5 count 5 ( 1) df_worklist_dataflow_doublequeue:n_basic_blocks 5 n_edges 5 count 5 ( 1) init_insns for 201: (insn_list:REG_DEP_TRUE 35 (nil)) init_insns for 205: (insn_list:REG_DEP_TRUE 15 (nil)) Pass 0 for finding pseudo/allocno costs a2 (r205,l0) best GR_REGS, cover GR_AND_ACC_REGS a1 (r204,l0) best GR_REGS, cover GR_AND_ACC_REGS a3 (r203,l0) best GR_REGS, cover GR_AND_ACC_REGS a5 (r202,l0) best GR_REGS, cover GR_AND_ACC_REGS a4 (r201,l0) best GR_REGS, cover GR_AND_ACC_REGS a7 (r200,l0) best GR_REGS, cover GR_AND_ACC_REGS a6 (r199,l0) best GR_REGS, cover GR_AND_ACC_REGS a0 (r194,l0) best GR_REGS, cover GR_AND_ACC_REGS a0(r194,l0) costs: MD1_REG:15660,15660 MD_REGS:15660,15660 ACC_REGS:15660,15660 GR_AND_MD0_REGS:5220,5220 GR_AND_MD1_REGS:15660,15660 GR_AND_ACC_REGS:15660,15660 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:10440,10440 MEM:15660 a1(r204,l0) costs: MD1_REG:7320,7320 MD_REGS:7320,7320 ACC_REGS:7320,7320 GR_AND_MD0_REGS:2440,2440 GR_AND_MD1_REGS:7320,7320 GR_AND_ACC_REGS:7320,7320 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:4880,4880 MEM:7320 a2(r205,l0) costs: MD1_REG:7320,7320 MD_REGS:7320,7320 ACC_REGS:7320,7320 GR_AND_MD0_REGS:2440,2440 GR_AND_MD1_REGS:7320,7320 GR_AND_ACC_REGS:7320,7320 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:4880,4880 MEM:7320 a3(r203,l0) costs: MD1_REG:7320,7320 MD_REGS:7320,7320 ACC_REGS:7320,7320 GR_AND_MD0_REGS:2440,2440 GR_AND_MD1_REGS:7320,7320 GR_AND_ACC_REGS:7320,7320 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:4880,4880 MEM:7320 a4(r201,l0) costs: MD1_REG:7320,7320 MD_REGS:7320,7320 ACC_REGS:7320,7320 GR_AND_MD0_REGS:2440,2440 GR_AND_MD1_REGS:7320,7320 GR_AND_ACC_REGS:7320,7320 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:4880,4880 MEM:7320 a5(r202,l0) costs: MD1_REG:7320,7320 MD_REGS:7320,7320 ACC_REGS:7320,7320 GR_AND_MD0_REGS:2440,2440 GR_AND_MD1_REGS:7320,7320 GR_AND_ACC_REGS:7320,7320 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:4880,4880 MEM:7320 a6(r199,l0) costs: MD1_REG:15660,15660 MD_REGS:15660,15660 ACC_REGS:15660,15660 GR_AND_MD0_REGS:5220,5220 GR_AND_MD1_REGS:15660,15660 GR_AND_ACC_REGS:15660,15660 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:10440,10440 MEM:15660 a7(r200,l0) costs: MD1_REG:12000,12000 MD_REGS:12000,12000 ACC_REGS:12000,12000 GR_AND_MD0_REGS:4000,4000 GR_AND_MD1_REGS:12000,12000 GR_AND_ACC_REGS:12000,12000 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:8000,8000 MEM:12000 Pass 1 for finding pseudo/allocno costs r205: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r204: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r203: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r202: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r201: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r200: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r199: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS r194: preferred GR_REGS, alternative GR_AND_ACC_REGS, cover GR_AND_ACC_REGS a0(r194,l0) costs: MD1_REG:15660,15660 MD_REGS:15660,15660 ACC_REGS:15660,15660 GR_AND_MD0_REGS:5220,5220 GR_AND_MD1_REGS:15660,15660 GR_AND_ACC_REGS:15660,15660 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:10440,10440 MEM:15660 a1(r204,l0) costs: MD1_REG:7320,7320 MD_REGS:7320,7320 ACC_REGS:7320,7320 GR_AND_MD0_REGS:2440,2440 GR_AND_MD1_REGS:7320,7320 GR_AND_ACC_REGS:7320,7320 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:4880,4880 MEM:7320 a2(r205,l0) costs: MD1_REG:7320,7320 MD_REGS:7320,7320 ACC_REGS:7320,7320 GR_AND_MD0_REGS:2440,2440 GR_AND_MD1_REGS:7320,7320 GR_AND_ACC_REGS:7320,7320 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:4880,4880 MEM:7320 a3(r203,l0) costs: MD1_REG:7320,7320 MD_REGS:7320,7320 ACC_REGS:7320,7320 GR_AND_MD0_REGS:2440,2440 GR_AND_MD1_REGS:7320,7320 GR_AND_ACC_REGS:7320,7320 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:4880,4880 MEM:7320 a4(r201,l0) costs: MD1_REG:7320,7320 MD_REGS:7320,7320 ACC_REGS:7320,7320 GR_AND_MD0_REGS:2440,2440 GR_AND_MD1_REGS:7320,7320 GR_AND_ACC_REGS:7320,7320 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:4880,4880 MEM:7320 a5(r202,l0) costs: MD1_REG:7320,7320 MD_REGS:7320,7320 ACC_REGS:7320,7320 GR_AND_MD0_REGS:2440,2440 GR_AND_MD1_REGS:7320,7320 GR_AND_ACC_REGS:7320,7320 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:4880,4880 MEM:7320 a6(r199,l0) costs: MD1_REG:15660,15660 MD_REGS:15660,15660 ACC_REGS:15660,15660 GR_AND_MD0_REGS:5220,5220 GR_AND_MD1_REGS:15660,15660 GR_AND_ACC_REGS:15660,15660 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:10440,10440 MEM:15660 a7(r200,l0) costs: MD1_REG:12000,12000 MD_REGS:12000,12000 ACC_REGS:12000,12000 GR_AND_MD0_REGS:4000,4000 GR_AND_MD1_REGS:12000,12000 GR_AND_ACC_REGS:12000,12000 M16_REGS:0,0 T_REG:0,0 PIC_FN_ADDR_REG:0,0 M16_T_REGS:0,0 LEA_REGS:0,0 GR_REGS:0,0 V1_REG:0,0 FP_REGS:8000,8000 MEM:12000 Insn 27(l0): point = 0 Insn 24(l0): point = 2 Insn 17(l0): point = 5 Insn 16(l0): point = 7 Insn 15(l0): point = 9 Insn 35(l0): point = 11 Insn 14(l0): point = 13 Insn 13(l0): point = 15 Insn 10(l0): point = 18 Insn 4(l0): point = 20 Insn 9(l0): point = 22 Insn 7(l0): point = 24 a0(r194): [18..20] [3..5] a1(r204): [6..7] a2(r205): [8..9] a3(r203): [8..13] a4(r201): [10..11] a5(r202): [14..15] a6(r199): [16..24] a7(r200): [19..22] Compressing live ranges: from 27 to 12 - 44% Ranges after the compression: a0(r194): [10..11] [0..1] a1(r204): [2..3] a2(r205): [4..5] a3(r203): [4..7] a4(r201): [6..7] a5(r202): [8..9] a6(r199): [10..11] a7(r200): [10..11] +++Allocating 64 bytes for conflict table (uncompressed size 64) ;; a0(r194,l0) conflicts: a6(r199,l0) a7(r200,l0) ;; total conflict hard regs: 31 ;; conflict hard regs: 31 ;; a1(r204,l0) conflicts: ;; total conflict hard regs: 31 ;; conflict hard regs: 31 ;; a2(r205,l0) conflicts: a3(r203,l0) ;; total conflict hard regs: 31 ;; conflict hard regs: 31 ;; a3(r203,l0) conflicts: a2(r205,l0) a4(r201,l0) ;; total conflict hard regs: 31 ;; conflict hard regs: 31 ;; a4(r201,l0) conflicts: a3(r203,l0) ;; total conflict hard regs: 31 ;; conflict hard regs: 31 ;; a5(r202,l0) conflicts: ;; total conflict hard regs: 31 ;; conflict hard regs: 31 ;; a6(r199,l0) conflicts: a0(r194,l0) a7(r200,l0) ;; total conflict hard regs: 31 ;; conflict hard regs: 31 ;; a7(r200,l0) conflicts: a0(r194,l0) a6(r199,l0) ;; total conflict hard regs: 31 ;; conflict hard regs: 31 cp0:a5(r202)<->a6(r199)@76:shuffle cp1:a3(r203)<->a5(r202)@76:shuffle cp2:a2(r205)<->a4(r201)@76:shuffle cp3:a1(r204)<->a3(r203)@76:shuffle cp4:a1(r204)<->a2(r205)@76:shuffle regions=1, blocks=5, points=12 allocnos=8 (big 0), copies=5, conflicts=2, ranges=9 **** Allocnos coloring: Loop 0 (parent -1, header bb0, depth 0) bbs: 4 3 2 all: 0r194 1r204 2r205 3r203 4r201 5r202 6r199 7r200 modified regnos: 194 199 200 201 202 203 204 205 border: Pressure: GR_AND_ACC_REGS=4 Reg 194 of GR_AND_ACC_REGS has 2 regs less Reg 204 of GR_AND_ACC_REGS has 2 regs less Reg 205 of GR_AND_ACC_REGS has 2 regs less Reg 203 of GR_AND_ACC_REGS has 2 regs less Reg 201 of GR_AND_ACC_REGS has 2 regs less Reg 202 of GR_AND_ACC_REGS has 2 regs less Reg 199 of GR_AND_ACC_REGS has 2 regs less Reg 200 of GR_AND_ACC_REGS has 2 regs less Pushing a5(r202,l0) Pushing a4(r201,l0) Pushing a3(r203,l0) Pushing a2(r205,l0) Pushing a1(r204,l0) Pushing a7(r200,l0) Pushing a6(r199,l0) Pushing a0(r194,l0) Popping a0(r194,l0) -- assign reg 2 Popping a6(r199,l0) -- assign reg 4 Popping a7(r200,l0) -- assign reg 3 Popping a1(r204,l0) -- assign reg 4 Popping a2(r205,l0) -- assign reg 2 Popping a3(r203,l0) -- assign reg 4 Popping a4(r201,l0) -- assign reg 2 Popping a5(r202,l0) -- assign reg 4 Disposition: 0:r194 l0 2 6:r199 l0 4 7:r200 l0 3 4:r201 l0 2 5:r202 l0 4 3:r203 l0 4 1:r204 l0 4 2:r205 l0 2 New iteration of spill/restore move +++Costs: overall -12750, reg -12750, mem 0, ld 0, st 0, move 0 +++ move loops 0, new jumps 0 insn=7, live_throughout: 28, 29, 31, 79, dead_or_set: 4, 199 insn=9, live_throughout: 28, 29, 31, 79, 199, dead_or_set: 200 insn=4, live_throughout: 28, 29, 31, 79, 199, 200, dead_or_set: 194 insn=10, live_throughout: 28, 29, 31, 79, 194, 199, dead_or_set: 200 insn=13, live_throughout: 28, 29, 31, 79, dead_or_set: 199, 202 insn=14, live_throughout: 28, 29, 31, 79, dead_or_set: 202, 203 insn=35, live_throughout: 28, 29, 31, 79, 203, dead_or_set: 201 insn=15, live_throughout: 28, 29, 31, 79, 203, dead_or_set: 201, 205 insn=16, live_throughout: 28, 29, 31, 79, dead_or_set: 203, 204, 205 insn=17, live_throughout: 28, 29, 31, 79, dead_or_set: 194, 204 insn=18, live_throughout: 28, 29, 31, 79, 194, dead_or_set: insn=24, live_throughout: 28, 29, 31, 79, dead_or_set: 2, 194 insn=27, live_throughout: 2, 28, 29, 31, 79, dead_or_set: init_insns for 201: (insn_list:REG_DEP_TRUE 35 (nil)) init_insns for 205: (insn_list:REG_DEP_TRUE 15 (nil)) changing reg in insn 4 changing reg in insn 17 changing reg in insn 24 changing reg in insn 7 changing reg in insn 13 changing reg in insn 9 changing reg in insn 9 changing reg in insn 10 changing reg in insn 35 changing reg in insn 15 changing reg in insn 13 changing reg in insn 14 changing reg in insn 14 changing reg in insn 16 changing reg in insn 16 changing reg in insn 17 changing reg in insn 15 changing reg in insn 16 deleting insn with uid = 24. try_optimize_cfg iteration 1 starting the processing of deferred insns ending the processing of deferred insns starting the processing of deferred insns ending the processing of deferred insns df_analyze called df_worklist_dataflow_doublequeue:n_basic_blocks 5 n_edges 5 count 5 ( 1) df_worklist_dataflow_doublequeue:n_basic_blocks 5 n_edges 5 count 5 ( 1) (note 1 0 5 NOTE_INSN_DELETED) (note 5 1 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK) (note 2 5 3 2 NOTE_INSN_DELETED) (note 3 2 7 2 NOTE_INSN_FUNCTION_BEG) (insn 7 3 9 2 (set (reg:SI 4 $4 [199]) (plus:SI (reg:SI 4 $4 [ i ]) (const_int -1 [0xffffffffffffffff]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:50 10 {*addsi3} (nil)) (insn 9 7 4 2 (set (reg:SI 3 $3 [200]) (leu:SI (reg:SI 4 $4 [199]) (const_int 4 [0x4]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:50 501 {*sleu_sisi} (nil)) (insn 4 9 10 2 (set (reg:DI 2 $2 [orig:194 D.2012+-4 ] [194]) (const_int 0 [0])) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:50 276 {*movdi_64bit} (expr_list:REG_EQUAL (const_int 0 [0]) (nil))) (jump_insn 10 4 11 2 (set (pc) (if_then_else (eq (reg:SI 3 $3 [200]) (const_int 0 [0])) (label_ref:DI 18) (pc))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:50 426 {*branch_equalitysi} (expr_list:REG_BR_PROB (const_int 3900 [0xf3c]) (nil)) -> 18) (note 11 10 13 3 [bb 3] NOTE_INSN_BASIC_BLOCK) (insn 13 11 14 3 (set (reg:DI 4 $4 [orig:202 csui.0+-4 ] [202]) (zero_extend:DI (reg:SI 4 $4 [199]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:50 181 {*zero_extendsidi2} (nil)) (insn 14 13 35 3 (set (reg:DI 4 $4 [203]) (ashift:DI (reg:DI 4 $4 [orig:202 csui.0+-4 ] [202]) (const_int 2 [0x2]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:50 405 {*ashldi3} (nil)) (insn 35 14 15 3 (set (reg/f:DI 2 $2 [201]) (high:DI (symbol_ref:DI ("CSWTCH.1") [flags 0x2] ))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:50 265 {*got_pagedi} (expr_list:REG_EQUIV (high:DI (symbol_ref:DI ("CSWTCH.1") [flags 0x2] )) (nil))) (insn 15 35 16 3 (set (reg/f:DI 2 $2 [205]) (lo_sum:DI (reg/f:DI 2 $2 [201]) (symbol_ref:DI ("CSWTCH.1") [flags 0x2] ))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:50 269 {*lowdi} (expr_list:REG_EQUIV (symbol_ref:DI ("CSWTCH.1") [flags 0x2] ) (nil))) (insn 16 15 17 3 (set (reg/f:DI 4 $4 [204]) (plus:DI (reg:DI 4 $4 [203]) (reg/f:DI 2 $2 [205]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:50 11 {*adddi3} (nil)) (insn 17 16 18 3 (set (reg:DI 2 $2 [orig:194 D.2012+-4 ] [194]) (sign_extend:DI (mem/s/u:SI (reg/f:DI 4 $4 [204]) [2 CSWTCH.1 S4 A32]))) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:50 202 {extendsidi2} (nil)) (code_label 18 17 19 4 8 "" [1 uses]) (note 19 18 27 4 [bb 4] NOTE_INSN_BASIC_BLOCK) (insn 27 19 34 4 (use (reg/i:DI 2 $2)) /home/member/kais58/beast/tgc/tgcware-for-irix/gcc46/src/gcc-4.6.1/gcc/testsuite/gcc.c-torture/unsorted/dump-noaddr.c:59 -1 (nil)) (note 34 27 36 NOTE_INSN_DELETED) (note 36 34 0 NOTE_INSN_DELETED)